A clocked flip-flop utilizes sequential logic to selectively latch one of two binary states, a logic "0" or a logic "1" Typical flip-flops of this type use a master and a slave section with the master section initially clocked on one edge of a clock signal to store the logic state on a master node and then, on the next edge of the clock, transfer this logic state to a slave node for storage therein. In this manner, on the next clock cycle, another logic state can be stored in the master node without affecting the slave node. These changes in the "latched" logic states are a function of the clock and the input data.
A typical D-flip-flop provides on the output a Q-output and a Q-Bar output. One measure of the speed of these flip-flops is the "clock-to-Q" time for the output Q to assume the logic state equal to the logic state of the data input, in response to the a transition of the clock signal. The delay between the time the data is input and the time that the Q-output is valid is a function of the amount of delay inherent in the internal structure of the flip-flop. This delay is due to the incorporation of such things as inverter circuits and transfer gates that are required to realize the various latch circuits and clock circuits internal to the flip-flop. It is desirable to not only reduce the number of components required to realize a flip-flop, but also to minimize the number of logic circuits required in the sequential configuration utilized in the flip-flop.